1. Field of the Invention
The present invention relates to an A/D conversion circuit and an image pick-up device provided with the A/D conversion circuit.
Priority is claimed on Japanese Patent Application No. 2011-050812, filed Mar. 8, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
FIG. 21 is a block diagram illustrating a partial configuration of a conventional A/D conversion circuit. FIG. 21 illustrates a unit of a conventional A/D conversion circuit for measuring a time, which is called a time to digital converter (TDC)-type A/D conversion circuit. The circuit illustrated in FIG. 21 includes a ring-like delay circuit 201 in which a plurality of delay elements NAND0 and INV1 to INV8 are connected to one another in a ring shape, a latch circuit 202 for holding the output of the ring-like delay circuit 201, a binarizing circuit (a full-encoder circuit) 203 for binarizing values held by the latch circuit 202, a counter circuit 204 for performing counting using one of the outputs of the ring-like delay circuit 201 as a count clock, and a memory circuit 205 for holding the output of the binarizing circuit 203 and the counter circuit 204.
Next, an A/D conversion operation will be described. FIG. 22 is a timing chart illustrating a conventional operation. FIG. 22 illustrates the operation timing of the circuit illustrated in FIG. 21. A logic state of a starting pulse StartP changes from an L state to an H state, so that the logic states of the delay elements constituting the ring-like delay circuit 201 sequentially change. Accordingly, a pulse circulates in the ring-like delay circuit 201. After a predetermined time has lapsed, the latch circuit 202 holds (latches) the output of the ring-like delay circuit 201. As illustrated in FIG. 22, the output of the ring-like delay circuit 201 corresponds to any one of nine states (state 0 to state 8). The output of the ring-like delay circuit 201 held (latched) by the latch circuit 202 is fully encoded (simultaneously encoded) by the binarizing circuit 203 to generate binarized data (a lower count value). The counter circuit 204 performs counting using the output of the delay element INV8 as a count clock to generate a count value (an upper count value). The lower count value and the upper count value are held in the memory circuit 205 to be output to the subsequent circuit as digital data.
The above-mentioned A/D conversion circuit is applied to, for example, an image pick-up device. Japanese Unexamined Patent Application, First Publication No. 2011-23887 discloses an example in which an A/D conversion circuit is arranged in a column unit provided to correspond to each of pixel columns to perform A/D conversion with respect to signals output from pixels.
FIG. 23 is a block diagram illustrating the configuration of a conventional image pick-up device. FIG. 23 illustrates a schematic configuration of a (C)MOS image pick-up device in accordance with a conventional example disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-23887. An image pick-up device 1001 includes an image capturing unit 1002, a vertical selection unit 1012, a read current source unit 1005, an analog unit 1006, a clock generation unit 1018, a ramp unit 1019, a column processing unit 1015, a horizontal selection unit 1014, an output unit 1017, and a control unit 1020. The image pick-up device 1001 is provided in column A/D conversion sections 1016 of the column processing unit 1015 thereof with a unit of the circuit illustrated in FIG. 21, and performs A/D conversion using the column A/D conversion sections 1016.
The control unit 1020 controls the vertical selection unit 1012, the read current source unit 1005, the analog unit 1006, the clock generation unit 1018, the ramp unit 1019, the column processing unit 1015, the horizontal selection unit 1014, the output unit 1017, and the like. The image capturing unit 1002 has a configuration in which unit pixels 1003 having photoelectric conversion elements are arranged in a matrix form, generates pixel signals corresponding to the amounts of incident electromagnetic waves, and outputs the pixel signals to vertical signal lines 1013 provided to columns.
The vertical selection unit 1012 controls row addresses or row scanning of the image capturing unit 1002 through row control lines 1011 when the unit pixels 1003 of the image capturing unit 1002 are driven. The horizontal selection unit 1014 controls column addresses or column scanning of the column A/D conversion sections 1016 of the column processing unit 1015. The read current source unit 1005 is a current source for reading the pixel signals from the image capturing unit 1002 as voltage signals. The analog unit 1006 performs amplification and the like according to necessity.
The column processing unit 1015 includes the column A/D conversion sections 1016 provided to the columns of the image capturing unit 1002. The column A/D conversion section 1016 converts an analog signal, which is the pixel signal output for each column from each unit pixel 1003 of the image capturing unit 1002, into digital data, and outputs the digital data. The clock generation unit 1018, for example, includes a ring-like delay circuit (corresponding to the ring-like delay circuit 201 of FIG. 21), and outputs a counter clock. The ramp unit 1019, for example, includes an integration circuit or a DAC circuit, and generates a reference signal which changes in an inclined manner through time.
The horizontal selection unit 1014 includes a shift register, a decoder and the like, and controls the column address or column scanning of each column A/D conversion sections 1016 in the column processing unit 1015. Accordingly, the A/D converted digital data is sequentially output to the output unit 1017 through horizontal signal lines.
Next, the configuration of the column A/D conversion section 1016 will be described. Each of the column A/D conversion sections 1016 has the same configuration, and includes a comparison unit 1110 and a counter 1101 (corresponding to the counter circuit 204 of FIG. 21).
The comparison unit 1110 includes a comparator circuit, and compares the pixel signal output from the unit pixel 1003 of the image capturing unit 1002 with the reference signal. For example, the comparison unit 1110 outputs a High level when the reference signal is larger than the pixel signal, and outputs a Low level when the reference signal is smaller than the pixel signal. The counter 1101 includes a binary counter circuit, and measures a comparison time until the comparison unit 1110 completes the comparison. Accordingly, a measurement value of the comparison time corresponding to the amplitude of the pixel signal is obtained as a count value of the counter 1101.
Next, the A/D conversion operation will be described. The detailed operation of the unit pixel 1003 will be omitted. However, a reset level and a signal level are output from the unit pixel 1003 as the pixel signal.
First, after the reset level is stably read from the unit pixel 1003, the comparison unit 1110 compares the reference signal with the pixel signal. The counter 1101 performs counting in an up-count mode, and a count value at the time of completion of the comparison is digital data of the reset level. Then, the count value of the counter 1101 is inverted.
Next, after the signal level is stably read from the unit pixel 1003, the comparison unit 1110 compares the reference signal with the pixel signal. The counter 1101 performs the counting in the up-count mode, and a count value of the counter 1101 at the time of completion of the comparison is digital data of a signal component (a signal obtained by subtracting the reset level from the signal level).
In the image pick-up device illustrated in FIG. 23, the counter 1101 corresponding to the counter circuit 204 illustrated in FIG. 21 performs the counting, so that an upper count value constituting an upper bit of digital data is obtained. However, since the image pick-up device has no configuration corresponding to the latch circuit 202 and the binarizing circuit 203 illustrated in FIG. 21, it is not possible to obtain a lower count value constituting a lower bit of digital data. Therefore, in the image pick-up device illustrated in FIG. 23, it is not possible to obtain digital data with high accuracy.
Circuits for obtaining an upper count value and a lower count value are arranged at units corresponding to the column A/D conversion sections 1016 of FIG. 23, so that it is possible to obtain digital data with high accuracy. As an example of such a circuit arrangement, an upper counter for obtaining the upper count value and a lower counter for obtaining the lower count value are considered to be arranged at the units corresponding to the column A/D conversion sections 1016.
In this case, the upper counter performs counting using one of output signals of a plurality of delay elements as a count clock, and the lower counter performs counting using a signal corresponding to the states of output signals of a plurality of delay elements as a count clock. When carry digit or shift-down digit has occurred in the most significant bit (MSB) of the lower count value counted by the lower counter, the upper counter performs counting using the MSB output signal of the lower counter as a count clock in order to adjust the upper counter value by the carry digit or shift-down digit.
Therefore, it is necessary to switch the counter clock input to the upper counter between one output signal of the plurality of delay elements and the MSB output signal of the lower counter. Hereinafter, the case in which the upper counter performs counting at the falling of the count clock (the upper counter performs counting when the count clock has changed from a High state (hereinafter referred to as an H state) to a Low state (hereinafter referred to as an L state)) will be described as an example.
The A/D conversion operation is an asynchronous operation, and a logic state of the count clock (one output signal of the plurality of delay elements) at a time point (a comparison completion time point) at which the comparison between the reference signal and the pixel signal has been completed is the H state or the L state. For example, when the logic state of the count clock at the comparison completion time point is the H state and a count clock in the L state is input from the lower counter to the upper counter through count clock switching, the logic state of the count clock changes from the H state to the L state before and after the switching, resulting in the occurrence of a phenomenon (erroneous count) in which the upper counter unnecessarily performs counting by one count. In other words, the erroneous count occurs due to the count clock switching input to the upper counter.